Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Shrinking/reducing device or field effect transistor (FET) feature sizes and, correspondingly, device minimum dimensions including horizontal dimensions (e.g., minimum channel length) and vertical dimensions (e.g., channel layer depth, gate dielectric thickness, junction depths and etc.) shrinks device size for increased device density and device performance, as well as reduces device operating conditions, i.e., chip and correspondingly, device supply voltages and voltage swings. Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency, i.e., performance. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
To minimize semiconductor circuit power consumption, most Integrated Circuits (ICs) are made in the well-known complementary insulated gate FET technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit and ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
In practice, however, typical FETs are much more complex than switches and transient power for circuit loads accounts for only a portion of CMOS chip power consumption. FET drain to source current (DC current and so, DC power consumed) is dependent upon circuit conditions and device voltages. Especially since device VT is directly proportional to gate dielectric thickness, as FET features (including gate dielectric and channel thickness) shrink, off FETs conduct what is known as subthreshold current, i.e., at gate biases below threshold for NFETs and above for PFETs. Further, for a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT. This is especially true in what is known as partially depleted (PD) or fully depleted (FD) silicon on insulator (SOI) technologies, where devices are formed in a thin uniform silicon surface layer. PD-SOI and FD-SOI FETs have suffered from dramatically increased subthreshold leakage to the point that, in some PD-SOI and FD-SOI IC chips it is the leakage dominant source.
Especially for complex chips and arrays with a large number of devices, device leakage (both gate and subthreshold) chip leakage power can be overwhelming, for PD-SOI and FD-SOI IC chips. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA). Thus, as chip features have shrunk, these leakage sources have become more prominent, especially for PD-SOI and FD-SOI IC chips. Approaches to increasing device VT to mitigate subthreshold leakage, e.g., with thicker gate dielectric or back biasing device channels for example, have been applied uniformly across all circuits on a PD-SOI and FD-SOI IC chip. Moreover, chip performance could be optimized while minimizing chip power, by allowing mixed circuits of different device types, i.e., PD-SOI, FD-SOI and bulk, rather than being constrained to using a single technology device for all circuits.
However, state of the art approaches to integrating these three disparate type of device technology devices on the same chip have not yielded satisfactory results. For example, a typical such state of the art approach would require at least two definition implants at two different energies and two different dose levels, one to define PD-SOI areas and a second to define FD-SOI areas in a chip location on a bulk wafer. Such a process requires two independent mask steps, one for each implant. Such a two step mask and implant carries with it critical alignment requirements to align to buried features at different depths, i.e., Buried OXide (BOX) at one depth in PD-SOI areas and at a second in FD-SOI areas. Unfortunately, each mask scatters oxygen ions, i.e., some ions passing through open mask patterns, randomly reflect of the vertical sides of the mask, scattering those ions as hey are implanted into the wafer. This scattering results in rough buried oxide with pronounced edges at the mask edges. When forming a thin uniform surface layer is critical for good device characteristics, such as for forming both PD-SOI and FD-SOI devices, irregularities in the underlying BOX can be disastrous. Further, any misalignment of the two masks is critical and could result in larger edge and boundary irregularities. There irregularities impact device density because devices cannot be placed in the vicinity. So, for example, as much as ten times (10×) the printable feature size may be lost along these boundaries. Consequently, the added complexity of multiple masked implants at different energies and dose levels in combination with implant scattering effects (i.e., BOX that is not well defined, not uniform and has pronounced edges) impacting device density, minimizes the usefulness of such an approach.
Thus, there is a need for a simple, reliable way to include PD-SOI and FD-SOI devices on bulk FET IC chips without severely impacting device density.